1. Field of the Invention
The present invention relates to a plasma doping system and a plasma doping method capable of dealing with larger-diameter wafers and of introducing impurities to a shallow depth with a lower energy level.
2. Description of the Related Art
In recent fabrication of ultra-high density semiconductor IC devices, one of the essential techniques which determines the main characteristics of transistors or other components is an impurity introduction technique for introducing conduction imparting type impurities (hereinafter, may be referred to simply as xe2x80x9cimpuritiesxe2x80x9d) into semiconductor substrates. It is indispensable for the impurity introduction technique to provide a high accuracy control of the dose of impurities or to form high density and very shallow impurity introduction regions. Note that the conduction imparting type impurities when introduced into a semiconductor layer serve to produce conductive p-type or n-type regions in the semiconductor layer, i.e., introduction region, as well as to vary the resistance value of the introduction region.
Conventional impurity introduction methods include a thermal diffusion method and an ion implantation method. Due to its accurate control of dosage, the ion implantation method is particularly advantageous. e.g., to control the threshold value of MOS FETs (Metal-Oxide-Semiconductor field effect transistors).
In the field of impurity introduction for forming high density and extremely shallow impurity introduction regions, particular attention has recently been given to a plasma doping method, in preference to the thermal diffusion method and the ion implantation method, since it is suitable for application to large diameter wafers.
The plasma doping method ensures a high throughput for the large diameter wafers and allows introduction of impurities at a low energy level, e.g., at room temperature.
Plasma doping systems for effecting such a plasma doping method are known from Japanese Patent Laid-open Pub. Nos. Hei 2-278720, Hei 5-16656, Hei 6-61161, etc.
Japanese Patent Laid-open Pub. No. Hei 5-16656 discloses an apparatus in which impurity gas plasma is generated between a pair of parallel plate electrodes to thereby perform the introduction of impurities. Japanese Patent Laid-open Pub. Nos. Hei 2-278720 and Hei 6-61161 disclose apparatuses in which an impurity gas plasma is generated by an ECR (Electron Cyclotron Resonance) method to thereby effect the introduction of impurities.
A plasma doping method using an ECR/RF plasma source is also disclosed in Semiconductor Integrated Circuit Technology 52th Symposium Transaction, pp. 165 to 170. June 1997. In this method, an He based B2H6 (diborane) gas is transformed into plasma for the introduction of boron into silicon substrates, after which RTA (Rapid Thermal Annealing) is carried out to form p-type diffusion regions having a surface density of approx. 1xc3x971021 cmxe2x88x923 and a depth of 50 nm.
In the case of selective introduction of impurities into the silicon substrate by use of the plasma doping method, it is necessary to form a resist film having openings corresponding to the impurity introduction regions so as to allow the impurities to be introduced through the openings of the resist film into the silicon substrate, and to thereafter remove the resist film, prior to annealing for the activation of the impurities.
With the increasing wafer diameters however, the conventional plasma doping apparatus using the ECR method has to be provided with an enlarged plasma generation chamber and impurity introduction chamber and with an enhanced power supply. For this reason, the overall dimensions of the system are increased including the ECR plasma source, i.e., a wave guide for microwaves, electromagnets and a matching unit, resulting in an increase in the floor area required for the placement of the plasma doping system itself.
In view of the system as a whole required for the introduction of impurities, there is a need for an ashing apparatus to remove the resist film acting as a mask and for an annealer, which necessitate a further increase in floor area for the placement of the system.
It is therefore the object of the present invention to provide a plasma doping system and a plasma doping method using the system, capable of reducing the floor areas required for the placement of the plasma doping system itself or or the placement of a plurality of apparatuses for a series of process steps attendant to the plasma doping.
The plasma doping system of the present invention is provided with a high-frequency power source for generating a helicon plasma of a gas containing conduction type impurities and antennas for discharging the high-frequency electric power.
In the case of larger wafer diameters, it is necessary for a plasma doping system using the ECR method for the generation of plasma to have a power source providing a frequency as high as 2.45 GHz or to enlarge the matching unit or the wave guides. In addition, the electromagnets for generating ECR must also be increased in size.
On the contrary, the system of the present invention allows use of a lower frequency, as low as 13.56 MHz, for the high-frequency power source, thereby eliminating the need to increase the size of the high frequency power source to a large extent. Due to the simple structure, the antennas need not be much enlarged either. Compact permanent magnets can be used as the magnetic field generation means disposed in the plasma flow passage/shaping thereby minimizing the size.
It is therefore possible for the doping system using the helicon plasma in accordance with the present invention to reduce the required floor area, as compared with the conventional doping system using the ECR plasma.
Furthermore, a single transfer chamber provides communication among the impurity introduction chamber, the ashing chamber and the annealing chamber of the plasma doping system, whereby a single system can perform a series of process steps attendant to the plasma doping such as introduction of conduction type impurities, removal of the resist mask for the selective introduction of the conduction type impurities and activation of the conduction type impurities.
Where separate apparatuses are used for different steps and individually placed, each apparatus requires a working space for the workers in addition to the floor area for the apparatus itself. Those apparatuses may be integrated into a single system such that conveyance robots carry the semiconductor substrate between the different chambers of the system, thereby achieving a reduction in the working space thereof. It is therefore possible to reduce the floor area necessary for the placement of the system in its entirety, as compared with the case of individual placement of each apparatus.